1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to an improved semiconductor device permitting stepped portions of the device to be reduced. The present invention also relates to an improved semiconductor device permitting improvement of registration precision.
2. Description of the Background Art
In a semiconductor device with a multi-layer interconnection structure, the interconnection layers are formed on different insulating layers. These interconnections are connected to conductive layers formed on the semiconductor substrate through contact holes provided in the insulating layers.
FIG. 15 is a plan view showing an example of such a semiconductor device with a multi-layer interconnection structure, a conventional dynamic random access memory. FIG. 16 is a cross sectional view taken along line 16--16 in FIG. 15.
Referring to these figures, the dynamic random access memory (DRAM) includes a semiconductor substrate 13. A field oxide film 12 for electrically isolating an active region 11 from the other active regions is provided in a main surface of semiconductor substrate 13. A gate electrode 1 is provided on semiconductor substrate 13 with a gate insulating film 14 therebetween. A pair of source/drain layers 15a, 15b are provided in the main surface of semiconductor substrate 13 on both sides of gate electrode 1. A first interlayer insulating film 2 is provided on semiconductor substrate 13, covering gate electrode 1. A first contact hole 10 for exposing a surface of one source/drain layer 15a is provided in first interlayer insulating film 2. A buried bit interconnection layer 4 is provided on first interlayer insulating film 2 so as to be electrically connected to one source/drain layer 15a through first contact hole 10. The upper part of buried bit interconnection layer 4 extends horizontally on the surface of first interlayer insulating film 2. A second interlayer insulating film 51 is provided on first interlayer insulating film 2, covering buried bit interconnection layer 4. A second contact hole 9 for exposing a surface of the other source/drain layer 15b is provided, penetrating through first interlayer insulating film 2 and second interlayer insulating film 51. A storage node interconnection 6 is provided on second interlayer insulating film 51 so as to be connected to the other source/drain layer 15b through second contact hole 9. A capacitor insulating film 16 covers a surface of storage node interconnection 6. A cell plate electrode 17 covers the surface of storage node interconnection 6 with capacitor insulating film 16 therebetween.
A method of manufacturing the DRAM shown in FIG. 16 will now be described.
Referring to FIG. 17, field oxide film 12 for isolating active region 11 from the other active regions is formed in the main surface of semiconductor substrate 13. Gate electrode 1 is formed on semiconductor substrate 13 with gate insulating film 14 therebetween. Pair of source/drain layers 15a, 15b are formed in the main surface of semiconductor substrate 13 on both sides of gate electrode 1 by means of implanting an impurity. First interlayer insulating film 2 is formed on semiconductor substrate 13 so as to cover gate electrode 1.
Referring to FIG. 18, photoresist 3 is formed on first interlayer insulating film 2. Photoresist 3 is patterned such that an opening 3a can be formed above one source/drain layer 15a.
Referring to FIGS. 18 and 19, first interlayer insulating film 2 is etched using photoresist 3 as mask, and first contact hole 10 for exposing a surface of one source/drain layer 15a is in first interlayer insulating film 2. Photoresist 3 is removed.
Referring to FIG. 20, a conductive layer 18 to form a buried bit interconnection to be electrically connected to one source/drain layer 15a through first contact hole 10 is formed. Photoresist 19 having a shape corresponding to the shape of the buried bit interconnection is formed on conductive layer 18.
Referring to FIGS. 20 and 21, conductive layer 18 is patterned using photoresist 19 as mask, and buried bit interconnection layer 4 is formed. Photoresist 19 is removed. Referring to FIG. 22, second interlayer insulating film 51 is formed on first interlayer insulating film 2, covering buried bit interconnection layer 4. Positive photoresist 20 is formed on second interlayer insulating film 51. A photomask 21 is placed on photoresist 20. Photomask 21 has a portion 21a for passing light toward the other source/drain layer 15b. Using photomask 21, light 22 is selectively directed to photoresist 20. Referring to FIG. 23, the part of resist 20 exposed with light is removed away by means of development.
Referring to FIGS. 23 and 24, using photoresist 20 as mask, second interlayer insulating film 51 and first interlayer insulating film 2 are etched, and second contact hole 9 for exposing a surface of the other source/drain layer 15b is formed. Photoresist 20 is then removed away.
Referring to FIG. 25, storage node interconnection 6 is formed on second interlayer insulating film 51 so as to be connected to the other source/drain layer 15b through second contact hole 9. A surface of storage node interconnection 6 is covered with capacitor insulating film 16. Covering storage node interconnection 6 with cell plate electrode 17 with capacitor insulating film 16 therebetween completes the conventional DRAM.
Thus manufactured conventional semiconductor devices with multi-layer interconnection structure are encountered with the following disadvantages.
More specifically, referring to FIGS. 22 and 26 in comparison, there will be a problem if misregistration of photomask 21 occurs when forming a second contact hole.
Misregistration of photomask 21 forms an opening shifted in photoresist 20. Etching first interlayer insulating film 2 and second interlayer insulating film 51 to form second contact hole 9 in this state exposes part of the surface of gate electrode 1 and part of the surface of buried bit interconnection layer 4 and partially removes field oxide film 12. Referring to FIGS. 27 and 28, if second contact hole 9 is formed shifted from the position as designed, and storage node interconnection 6 is connected to the other source/drain layer 15b, storage node interconnection 6 may be electrically connected to gate electrode 1 and buried bit interconnection layer 4 as well, or field oxide film 12 is partially removed, resulting in current leakage. The reliability of the DRAM thus decreases. The above-described method therefore strictly requires high registration precision.
Referring to FIG. 16, since buried bit interconnection layer 4 extends on first interlayer insulating film 2, stepped portions are generated, which makes difficult subsequent patterning of interconnections.